1. Field of the Invention
The present invention relates to pipelined analog-to-digital converters. In particular, the present invention relates to the correction of conversion errors in pipelined analog-to-digital converters.
2. Description of Related Art
Pipelined analog-to-digital converters (ADC's) require adders to generate the correct digital output where the digital outputs of the preceding stages are delayed, scaled, and added relative to the digital outputs of the subsequent stages.
The subsequent stages represent the correction of the preceding stages. The adders in the subsequent stages are used to correct or adjust the result of the analog-to-digital conversion in the preceding stages and at the same time introduce the additional resolution bits. The correction or adjustment is added to the preceding value. This correction value may be a positive number or a negative number. Using 2's complement arithmetic, a negative number is sign extended before the addition.
Prior art methods employ N adders for an N-stage pipelined ADC to perform the digital correction. The size of each adder is a function of the significance of the pipeline stage. As more resolution bits are added when the pipeline stages go to less and less significant bits, the size of the adders becomes larger and larger. The area for realizing the adders becomes significant. For example, a four-stage pipelined ADC with 4-bits per stage requires 4 adders: a 7-bit adder in the first stage, a 10-bit adder in the second stage, a 13-bit adder in the third stage, and a 19-bit adder in the fourth and last stage. Each N-wide adder takes 1 half adder and N-1 full adders. A half adder takes one XOR gate and one AND gate; a full adder takes two XOR gates, two AND gates, and one OR gate. The total amount of hardware for the digital correction is, therefore, significant.
Accordingly, it is desirable to have a method and apparatus to provide the digital correction in a pipelined ADC with a smaller integrated circuit area and having less complexity.